Process for forming both split gate and common gate finfet transistors and integrated circuits therefrom

ABSTRACT

A method to fabricate an integrated circuit (IC) that includes a plurality of MOSFETs including at least one common gate FinFET device and at least one split gate FinFET device. A substrate having a semiconductor surface is provided. A plurality of fins are formed from the semiconductor surface including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height. Gate slacks are formed on the taller and shorter fins such that a gate electrode for the taller fin is a split gate electrode and a gate electrode for the shorter fin is a common gate electrode. Fabrication of the IC is completed, wherein the split gate FinFET includes the split gate electrode and the common gate FinFET device includes the common gate electrode. An IC includes a substrate having a semiconductor surface, a plurality of semiconductor fins including at least one taller fin of a first height and at least one shorter fin of a second height, wherein the first height is at least 10% greater than the second height, and at least one common gate FinFET device formed from the shorter fin and at least one split gate FinFET device providing a parallel gate transistor pair comprising a first and a second transistor formed from the taller fin.

FIELD OF THE INVENTION

Embodiments of the present invention generally relate to MOSFETtransistors and more particularly to the fin-type MOSFET transistorscommonly known as FinFETs, and to methods for forming integratedcircuits (ICs) including at least one fin which provides a split gateFinFET and at least one fin which provides a conventional common gateFinFET.

BACKGROUND

Field effect transistors (FETs) can be formed in a variety of ways toserve a variety of purposes for integrated circuits and other devices.Commonly, FETs are formed as “planar” devices in many integratedcircuits, i.e., as devices in which the conduction channel has width andlength extending in a direction parallel to the major surface of asubstrate. FETs can be formed in a semiconductor-on-insulator (SOI)layer of a substrate or in a bulk semiconductor substrate.

Frequently, FETs are formed having a non-planar conduction channel, inorder to serve a special purpose. In such non-planar FETs, either thelength or the width of the transistor channel is oriented in thevertical direction, that is, in a direction perpendicular to the majorsurface of the substrate. In one such type of device, commonly referredto as the FinFET, the width of the conduction channel is oriented in thevertical direction, while the length of the channel is oriented parallelto the major surface of the substrate. With such orientation of thechannel, FinFETs can be constructed to have a larger width conductionchannel than planar FETs so as to produce larger current drive thanplanar FETs which occupy the same amount of integrated circuit area (thearea parallel to the major surface of the substrate).

As known in the art, improved circuit performance or function can oftenbe provided by providing extra transistors. For example, in SRAM celldesigns, there are known benefits to having dual pass gate devices, suchas to optimize read and write configurations, and for compensating forprocess corners. However, as well known in the art, the cost for ICs isgenerally based on their die area. Accordingly, adding extra transistorsto a conventional IC design adds to the cost of the circuit. Hence, itis desirable to be able to add transistors to an IC design withoutadding any significant additional die area and thus additional die cost.

SUMMARY

This Summary is provided to comply with 37 C.F.R. §1.73, presenting asummary of the invention briefly indicating the nature and substance ofthe invention. It is submitted with the understanding that it will notbe used to interpret or limit the scope or meaning of the claims.

A method to fabricate an integrated circuit (IC) that includes aplurality of MOSFETs including at least one common gate FinFET deviceand at least one split gate FinFET device. A substrate having asemiconductor surface is provided. A plurality of semiconductor fins areformed from the semiconductor surface including at least one taller finof a first height and at least one shorter fin of a second height,wherein the first height is at least 10% greater than the second height.Gate stacks are formed on the taller and shorter fins such that a gateelectrode for the taller fin is a split gate electrode and a gateelectrode for the shorter fin is a common gate electrode. Fabrication ofthe IC is completed, wherein the split gate FinFET includes the splitgate electrode and the common gate FinFET device includes the commongate electrode.

The gate electrode can be polysilicon comprising, Selective fin etchingcan be used to reduce the height of a portion of the fins to form one ormore of shorter fins. A planarization process, such as but not limitedto chemical mechanical planarization (CMP) and its variants, can be usedto form a gate electrode for the taller fin that is a split gateelectrode and a gate electrode for the shorter fin that is a common gateelectrode.

As noted above, in SRAM cell designs, there are benefits to having dual(split) pass gate devices, such as for example to optimize read andwrite operations, and to compensate for process corners. This istypically not an option in conventional bulk silicon comprisingsubstrates due to the resulting increase in die area and increase in diecost. However, in certain embodiments of the invention FinFETs are used,where the new split gate FinFET architecture provides paralleltransistors formed from the same fin, using the same or nearly the samedie area used by a conventional FinFET. The actual area needed dependson the configuration. Since contacts need a certain amount of space,generally in current designs being positioned on a flat surface, a bitmore area may be added due to the contact for the second gate. However,sidewall contacts can allow the split gate FinFET architecture to usethe same area used by a conventional common gate FinFET.

A variety of ICs can benefit from the area efficient combination of atleast one split gate FinFET and at least one common gate FinFET device.In one IC embodiment that includes one or more SRAM arrays, the SRAMarray uses a combination of at least one split gate FinFET and at leastone common gate FinFET device. Applied to SRAMs, use of a split gateFinFET with a separate Word line coupled to the gate of each of itsgates can provide variable read and write currents to SRAM cells withoutan increase in cell-size. Combining conventional common gate and splitgate FinFETs according to embodiments of the invention on the same ICcan be applied beyond SRAMs. For example, the extra gate provided by thesplit gate FinFET can be used for back gate biasing the other transistorprovided by the split gate FinFET, such as for reducing the input offsetvoltage (VIO) for a differential amplifier, or be used in othercircuitry that can benefit from the addition of back-gate biasing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A-H shows resulting intermediate cross sectional depictionsassociated with a method for fabricating an integrated circuit (IC)comprising a plurality of MOSFETs including at least one conventionalcommon gate FinFET device and at least one split gate FinFET device,according to an embodiment of the invention.

FIG. 2A shows a circuit schematic for a 5T SRAM cell modified to includea parallel gate pass formed from a split gate FinFET device, accordingto an embodiment of the invention.

FIG. 2B shows a circuit schematic for a 6T SRAM cell modified to includeadd a second parallel pass gate formed from another split gate FinFETdevice, so that parallel pass gates are associated with each of thecontrol nodes, according to an embodiment of the invention.

FIG. 2C is a schematic of an integrated circuit comprising a memoryarray having a plurality of 5T SRAM cells, according to an embodiment ofthe invention.

FIG. 3 shows a circuit schematic for an operational amplifier having oneof the input differential pair transistors formed from a split gateFinFET device to provide parallel gates, operable to use on back gatebias on one of the parallel gates for mismatch correction, according toanother embodiment of the invention.

DETAILED DESCRIPTION

The present invention is described with reference to the attachedfigures, wherein like reference numerals are used throughout the figuresto designate similar or equivalent elements. The figures are not drawnto scale and they are provided merely to illustrate the instantinvention. Several aspects of the invention are described below withreference to example applications for illustration. It should beunderstood that numerous specific details, relationships, and methodsare set forth to provide a full understanding of the invention. Onehaving ordinary skill in the relevant art, however, will readilyrecognize that the invention can be practiced without one or more of thespecific details or with other methods. In other instances, well-knownstructures or operations are not shown in detail to avoid obscuring theinvention. The present invention is not limited by the illustratedordering of acts or events, as some acts may occur in different ordersand/or concurrently with other acts or events. Furthermore, not allillustrated acts or events are required to implement a methodology inaccordance with the present invention.

FIG. 1A-H show resulting intermediate cross sectional depictionsassociated with a method 100 for fabricating an integrated circuit (IC)comprising a plurality of MOSFETs including at least one conventionalcommon gate FinFET device and at least one split gate FinFET device,according to an embodiment of the invention. FIG. 1A shows the resultingcross section after step 101 which comprises providing a substrate 150having a semiconductor surface 153. Substrate 150 can comprise a bulksilicon comprising substrate or a variety of SOI substrates. In the caseof a bulk silicon comprising substrate 150, trench isolation (not shown)will generally be provided.

Substrate 150 in FIG. 1A is shown as an SOI substrate comprising asilicon surface 153 on a dielectric layer 152. A conventional SOIsubstrate comprises a relatively thick semiconductor support layer 151(e.g. 200 to 600 μm thick) having a dielectric layer 152 thereon, and athin semiconductor surface layer 153 (e.g. silicon) on the dielectriclayer 152 upon which one or more transistors are formed persemiconducting region. The surface semiconductor layer for a SOIsubstrate is generally 30 to 400 nm thick. The dielectric layer 152 cancomprise a silicon oxide, such as silicon dioxide.

FIG. 1B shows the resulting cross section after step 102 which comprisesforming a plurality of semiconductor fins from the semiconductor surface153. The height of the fins is shown as “h”, FIG. 1C shows the resultingcross section after step 103 which comprises providing at least onetaller fin 157 and at least one shorter fin 156. In one embodiment, theproviding step can comprise selective etching, wherein the selectiveetching can comprise masking fin(s) that will become taller fin 157(having a first height shown as “h”) with a masking material, andetching the other fin(s) to form at least one shorter fin 156 having asecond height shown as “h′”. The masking material can comprises a hardmask layer such as SiON, SiON, or SiC or photoresist. In the selectiveetching embodiment the first height shown in FIG. 1C as “h” correspondsto the thickness of surface semiconducting layer 153. However, in otherembodiments of the invention h″ does not correspond to the thickness ofsurface semiconducting layer 153.

The first height is at least 10% greater than the second height, such as20% greater, 30% greater, 40% greater or 50% greater. In one exemplaryembodiment, the first height h=90 to 100 nm and the second height h′=40to 60 nm.

FIG. 1D shows the resulting cross section after step 104 which comprisesforming a gate stack on the taller fin(s) 157 and shorter fin(s) 156such that a gate electrode for the taller fin 157 is a split gateelectrode and a gate electrode for the shorter fin 156 is a common gateelectrode. Step 104 can comprise forming a gate dielectric layer 158 onthe taller fin 157 and the shorter fin 156.

FIG. 1E shows the resulting cross section after step 105 which comprisesforming a gate electrode layer 159 on the gate dielectric layer 158 onboth the taller fin 157 and the shorter fin 156. The gate electrodelayer 159 can comprise polysilicon, for example. In one embodiment, thethickness of the gate electrode layer 159 can be 50 to 200 nm.

FIG. 1F shows the resulting cross section after step 106 which comprisesa planarization process, such as but not limited to chemical mechanicalplanarization (CMP) and its variants can be used to form a gateelectrode for the taller fin 157 that is a split gate electrode and agate electrode for the shorter fin 156 that is a common gate electrode.Other planarization techniques, such as disclosed in U.S. Pat. No.5,629,224 such as resist/etchback planarizing techniques, forfabricating semiconductor devices may also generally be used. U.S. Pat.No. 5,629,224 is incorporated by reference into the present applicationfor its planarization teachings.

The planarization process removes the gate electrode layer 159 from atop of the taller fins 157 to remove the topside gate electrode layer159 and thus the electrical connection between the first gate 159(a) andsecond gate 159(b) which are located on the first and second sidewallsof the taller fins 157. This forms the gate structure for a split gateFinFET device. The gate electrode layer 159 on a top of the shorter fins156 remains following CMP to maintain the topside gate electrode layer159 electrically connection of the gate electrode layer 159 on first andsecond side walls of the shorter fins 156, thus forming the gatestructure for a common gate FinFET device. Top views of the respectivestructures are provided in FIG. 1F for added clarity. In the case of apolysilicon comprising gate electrode layer 159, the step of silicidingthe gate electrode layer after CMP or other planarization process can beincluded.

FIG. 1G shows the resulting cross section after step 107 in which thegate electrode layer 159 is patterned to form a patterned gate electrodelayer. FIG. 1H shows the resulting cross sections after fabrication isthen completed in step 108, generally including conventional stepsincluding LDD, spacer, source/drain, and multi-layer metallizationprocessing. Following completion of fabrication, as shown in FIG. 1H, atleast one conventional common gate FinFET device 170 comprising a commongate 160 and common source 181 and common drain 182 is formed from theshorter fin 156 and at least one split gate FinFET device 180 comprisingelectrically isolated (split) gates 159(a) and 159(b) and common source171 and common drain 172 is formed from the taller fin 157. The splitgate FinFET device 3 80 can be seen to generally retain the same area ascommon gate FinFET device 170, but provides an extra transistor gate.

In one embodiment of the invention, replacement gate processing isincluded. The replacement gate process comprises removing the patternedgate electrode layer, such as a polysilicon comprising layer, associatedwith at least a portion of the plurality of MOS transistors to form aplurality of trenches, and filling the trenches with a metal comprisingreplacement gate electrode layer to form replacement metal gatetransistors. As known in the art, different metal gate materials (havingappropriate work functions) are generally used for PMOS and NMOS deices.Planarization processing generally follows after replacement gate metaldeposition.

FIG. 2A shows a circuit schematic for a 5T SRAM cell 200 formed on asubstrate 201 modified to include a parallel gate pass gate 221comprising gates M5 a and M5 b formed from a split gate FinFET deviceaccording to an embodiment of the invention. Cell 200 comprises a corestorage element 202 comprising cross coupled first and second inverters207 comprising M1 and M2 and 208 comprising M3 and M4, respectively,having a first storage node 211 and a second complementary storage node212, and power supply traces Vdd and Vss coupled to the cell 200. Thecore storage element 202 comprising M1-M4 is shown utilizingconventional single common gate FinFET devices. The source or drain ofparallel gate pass gate 205 is shown coupled to receive a BL signal,with the other of the source or drain coupled to the first storage node211. A first wordline WL1 is coupled to the first gate M5 a and a secondwordline WL2 is shown coupled to the second gate M5 b.

WL1 and WL2 can be used together or separately. The separate word linesWL1 and WL2 can both be used for writing, where there is a need toovercome the current cell state. Generally for reading, one of WL1 andWL2 is used. However, if read speed is important, WL3 and WL2 may bothbe used for read.

Signals applied to WL1 and WL2 can be in a digital form (neither, one orboth on), or in a digital/analog combination, where the channel ismodulated to optimize the SRAM characteristics. For example, one of theparallel gates can be used as an analog bias, while the other isswitched (e.g. digital). The parallel mode provided by the parallel passgates M5 a and M5 b can have one of these gates used for programming(Writing) with the other of these gates used for Reading. Thisarrangement can provide several potential advantages, such as providinga level of programmability to account for process variability. Thisarrangement can also provide different read and write pass gateresistances by having M5 a and M5 b have structural or dopingdifferences.

For example, by selectively implanting one of the channel regionsassociated with M5 a or M5 b, the paralleled transistors M5 a or M5 bcan be designed to have different strengths, providing added designflexibility. For example, it is possible to selectively dope the channelregions of each side of the gate, such as with angled implants. This canbe used to skew the effect of the respective parallel devices.

FIG. 2B shows a circuit schematic for a 6T SRAM cell 250 modified toinclude add a second parallel pass gate formed from another split gateFinFET device, so that parallel pass gates are associated with each ofthe control nodes 213 and 212, according to an embodiment of theinvention. Cell 250 includes a second pass gate 231 utilizing a secondsplit gate FinFET device, the second pass gate 231 having split gate M6a and M6 b and a common source and a drain, wherein the common source ordrain of second pass gate 231 is coupled to the second storage node 212.A second complementary bitline (BL-bar) is coupled to the other of thecommon source or drain of the second pass gate 231. The first wordline(WL1) is shown coupled to gate M6 a of second pass gate 231 and thesecond wordline (WL2) is coupled to gate M6 b of second pass gate 231.

FIG. 2C is a schematic of an IC 270 formed on a substrate 201 comprisinga memory array 260 comprising a plurality of 5T SRAM cells 200,according to an embodiment of the invention. Bit line select controller171 receives a read/write signal 178 at its input indicating whether aread or write operation is to be performed and the column or bit lineaddress. The bit line select controller 171 also receives a data insignal 175 in the case of a write operation and provides a data outsignal 176 in the case of a read operation. An output of the BLcontroller 171 is also coupled to BLs shown as BL1 and BL2. WL selectcontroller 172 receives the read/write signal 178 at its inputindicating whether a read or write operation is to be performed. Theoutput of the WL controller 172 is coupled to WL1 and WL2.

FIG, 3 shows a circuit schematic for an operational amplifier 300 havingan input differential pair comprising M7 and M8, with M8 formed from asplit gate FinFet device to provide back gate bias, according to anotherembodiment of the invention. The gate of M7 is shown receiving inputsignal A. M8 has parallel gates provided by a split gate FinFet deviceaccording to an embodiment of the invention comprising a conventionalgate electrode 311 operable to receive input signal B, and a back gateelectrode 316 operable to receive a DC bias voltage shown as VDAC. Theback gate electrode can be coupled to a back gate bias shown as VDAC,such as for reducing the input offset voltage (VIO) for the differentialamplifier, or be used in other circuitry that can benefit from back-gatebiasing. Having a back gate allows the split gate FinFET device toutilize the “Back-gate bias effect” or “Body effect” to modify thresholdvoltage. For example, as known in the art, in the case of NMOS, the Vtcan be increased for a +ve source-to-bulk voltage, where the back gatecan modulate the body voltage.

Other circuits having parallel transistors can benefit from embodimentsof the invention by being able to shrink the die area. For example, thePMOS paralleled pullup transistor pair for conventional CMOS NAND gatecomprising logic and the NMOS paralleled pulldown transistor pair forconventional CMOS NOR gate comprising logic can both be realized usingthe new split gate FinFET architecture formed from the same Fin asdescribed above, with one or more other transistors in the circuitembodiment using conventional common gate FinFETs.

While various embodiments of the present invention have been describedabove, it should be understood that they have been presented by way ofexample only, and not limitation. Numerous changes to the disclosedembodiments can be made in accordance with the disclosure herein withoutdeparting from the spirit or scope of the invention. Thus, the breadthand scope of the present invention should not be limited by any of theabove described embodiments. Rather, the scope of the invention shouldbe defined in accordance with the following claims and theirequivalents.

Although the invention has been illustrated and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others skilled in the art upon the reading andunderstanding of this specification and the annexed drawings. Forexample, there can be two series coupling capacitors instead of one. Inaddition, while a particular feature of the invention may have beendisclosed with respect to only one of several implementations, suchfeature may be combined with one or more other features of the otherimplementations as may be desired and advantageous for any given orparticular application.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. Furthermore, to the extent that the terms “including”,“includes”, “having”, “has”, “with”, or variants thereof are used ineither the detailed description and/or the claims, such terms areintended to be inclusive in a manner similar to the term “comprising.”

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

The Abstract of the Disclosure is provided to comply with 37 C.F.R.§1.72(b), requiring an abstract that will allow the reader to quicklyascertain (he nature of the technical disclosure. It is submitted withthe understanding that it will not be used to interpret or limit thescope or meaning of the following claims.

1. A method to fabricate an integrated circuit (IC) comprising aplurality of MOSFETs including at least one common gate FinFET deviceand at least one split gate FinFET device, comprising: providing asubstrate having a semiconductor surface; forming a plurality ofsemiconductor fins from said semiconductor surface comprising at leastone taller fin of a first height and at least one shorter fin of asecond height, wherein said first height is at least 10% greater thansaid second height; and forming gate stacks on said taller and saidshorter fin such that a gate electrode for said taller fin is a splitgate electrode and a gate electrode for said shorter fin is a commongate electrode, and completing fabrication of said IC, wherein saidsplit gate FinFET includes said split gate electrode and said commongate FinFET device includes said common gate electrode.
 2. The method ofclaim 1, wherein said substrate comprises a SOI substrate.
 3. The methodof claim 1, wherein said substrate comprises a bulk silicon comprisingsubstrate.
 4. The method of claim 1, wherein said forming gate stackscomprises planarization processing to remove said gate electrode from atop of said taller fin, but not completely remove said gate electrodefrom a top of said shorter fin,
 5. The method of claim 4, wherein saidplanarization processing comprises chemical mechanical polishing (CMP).6. The method of claim 1, wherein said split gate electrode and saidcommon gate electrode comprise polysilicon.
 7. The method of claim 1,further comprising the steps of: removing said gate electrode on saidtaller fin and said gate electrode on said shorter fin to formrespective trenches, and filling said respective trenches with a metalcomprising replacement gate electrode layer to form replacement metalgates.
 8. The method of claim 3, wherein said forming said plurality offins from said surface comprising at least one taller fin and at leastone shorter fin comprises selective etching, said selective etchingcomprising masking said taller fin with a masking material.
 9. Themethod of claim 1, wherein said split gate FinFET comprises a paralleltransistor pair comprising a first transistor and a second transistor,further comprising the step of differentially doping a channel regionassociated with said first transistor as compared to a channel region ofsaid second transistor.
 10. The method of claim 1, wherein said firstheight is between 20% greater and 200% greater than said second height.11. A method to fabricate an integrated circuit (IC) comprising aplurality of MOSFETs including at least one common gate FinFET deviceand at least one split gate FinFET device, comprising: providing asubstrate having a semiconductor surface; etching said semiconductorsurface to form a plurality of semiconductor fins; selectively etchingsaid plurality of fins to form at least one taller fin of a first heightand at least one shorter fin of a second height, wherein said firstheight is at least 10% greater than said second height; forming a gatedielectric layer on said taller fin and said shorter fin; forming a gateelectrode layer on said gate dielectric layer on said taller fin andsaid shorter fin; chemical mechanical polishing (CMP) to remove saidgate electrode layer from a top of said taller fin to form is a splitgate electrode, and said gate electrode layer is maintained on a top ofsaid shorter fin to form a common gate electrode; patterning said gateelectrode layer following said CMP, and completing fabrication of saidIC, wherein said split gate FinFET includes said split gate electrodeand said common gate FinFET device includes said common gate electrode.12. An integrated circuit (IC), comprising: a substrate having asemiconductor surface, said semiconductor surface comprising a pluralityof semiconductor fins including at least one taller fin of a firstheight and at least one shorter fin of a second height, wherein saidfirst height is at least 10% greater than said second height; and leastone common gate FinFET device formed from said shorter fin, said commongate FinFET device having a gate electrode layer providing a singlecommon gate extending from first a sidewall to a top to a secondsidewall of said shorter fin, at least one split gate FinFET deviceproviding a parallel gate transistor pair comprising a first and asecond transistor formed from said taller fin, said split gate FinFETdevice having a first gate electrode on a first sidewall of said tallerfin to form a first gate for said first transistor and a second gateelectrode electrically isolated from said first gate electrode on asecond sidewall of said taller fin to form a second gate for said secondtransistor.
 13. The IC of claim 12, wherein said IC comprises an arrayof memory cells comprising a plurality of SRAM cells, said SRAM cellseach comprising: a core storage element comprising cross coupled firstand second inverters having a first storage node and a secondcomplementary storage node, said core storage element utilizing aplurality of said common gate FinFET devices; at least a first pass gateutilizing said split gate FinFET including said first gate and saidsecond gate having a common source and a common drain, wherein saidcommon source or said common drain are coupled to said first storagenode; at least a first bitline (BL) coupled the other of said source orsaid drain of said first pass gate; a first wordline (WL1) coupled tosaid first gate of said first pass gate and a second wordline (WL2)coupled to said second gate of said first pass gate.
 14. The IC of claim13, wherein said at least one split gate FinFET device comprises aplurality of said split gate FinFET devices, further comprising: asecond pass gate utilizing one of said plurality of split gate FinFETdevices, said second split gate FinFET device including a first gate andsecond gate and a common source and a common drain, wherein said commonsource or drain of said second pass gate is coupled to said secondstorage node; a second complementary bitline (BL-bar) coupled to theother of said common source or said drain of said second pass gate;wherein said first wordline (WL1) is coupled to said first gate of saidsecond pass gate and said second wordline (WL2) is coupled to saidsecond gate of said second pass gate.
 15. The IC of claim 12, furthercomprising circuitry comprising an input stage including a differentialpair comprising first and second input transistors and an output stagecoupled to said input stage, said output stage providing an output,wherein at least one of said first and second input transistors utilizesaid split gate FinFET device, wherein said first gate of said firstinput transistor is coupled to receive an input signal and said secondgate of said second input transistor is coupled to a power supply lineoperable to receive a DC bias voltage for mismatch correction of saidcircuitry.
 16. The IC of claim 15, wherein said circuitry comprises anoperational amplifier and said mismatch correction comprises reducing aninput offset voltage for said operational amplifier.
 17. A method ofoperating an array of memory cells comprising a plurality of SRAM cells,said SRAM cells in said array each comprising a core storage elementcomprising cross coupled first and second inverters utilizing aplurality of common gate FinFET devices having a first storage and asecond complementary storage node and at least a first pass gateutilizing a first split gate FinFET device providing a parallel gatetransistor pair having a common source and a common drain comprising afirst transistor having a first gate and a second transistor having asecond gate coupled to said first storage node, at least a first bitline(BL) coupled to said source or said drain of said first pass gate, and afirst wordline (WL1) coupled to said first gate and a second wordline(WL2) coupled to said second gate, said method comprising: coupling afirst signal to said WL1 and a second signal different from said firstsignal to said WL2 for at least one operation for said array of memorycells.
 18. The method of claim 17, wherein at least one of said firstsignal and said second signal comprise a digital signal.
 19. The methodof claim 18, wherein said digital signal is coupled to said WL1 and ananalog signal is coupled to said WL2.